10 mhz, 20 v/s, g = 1, 10, 100, 1000 i cmos ? programmable gain instrumentation amplifier preliminary technical data ad8253 rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features small package: 10-lead msop programmable gains: 1, 10, 100, 1000 digital or pin-programmable gain setting wide supply: 5 v to 15 v excellent dc performance high cmrr 120 db , g = 100 low gain drift: 10 ppm/c low offset drift: 1.2 v/c , g = 1000 excellent ac performance fast settling time: 615 ns to 0.001% high slew rate: 20 v/s low distortion: high cmrr over frequency: 80 db to 50 khz low noise: 8 nv/hz, g = 1000 low power: 4 ma applications data acquisition biomedical analysis test and measurement general description the ad8253 is an instrumentation amplifier with digitally programmable gains that has g input impedance, low output noise, and low distortion making it suitable for interfacing with sensors and driving high sample rate analog-to-digital converters (adcs). it has high bandwidth of 10 mhz, low thd and fast settling time of 615 ns to 0.001%. offset drift and gain drift are specified to 1.2 v/c and 10 ppm/c, respectively for g = 1000. in addition to its wide input common voltage range, it boasts a high common-mode rejection of 80 db at g = 1 from dc to 50 khz. the combination of precision dc performance coupled with high speed capabilities make the ad8253 an excellent candidate for data acquisition. furthermore, this monolithic solution simplifies design and manufacturing, and boosts performance of instrumentation by maintaining a tight match of internal resistors and amplifiers. the ad8253 user interface consists of a parallel port that allows users to set the gain in one of two different ways (see figure 1 for the functional block diagram). a 2-bit word sent via a bus can be latched using the wr input. an alternative is to use transparent gain mode where the state of logic levels at the gain port determines the gain. functional block diagram a1 a0 dgd wr logic ad8253 out +vs -vs ref +in -in figure 1. table 1. instrumentation and difference amplifiers by category high performance low cost high voltage mil grade low power digital gain ad8220 1 ad623 1 ad628 ad620 ad627 1 ad8231 1 ad8221 ad8553 1 ad629 ad621 ad8250 ad8222 ad524 ad8251 ad8224 1 ad526 ad8555 1 ad624 ad8556 1 ad8557 1 1 rail-to-rail output. the ad8253 is available in a 10-lead msop package and is specified over the ?40c to +85c temperature range, making it an excellent solution for applications where size and packing density are important considerations.
ad8253 preliminary technical data rev. pra | page 2 of 10 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing diagram ........................................................................... 5 absolute maximum ratings............................................................ 6 maximum power dissipation ......................................................6 esd caution...................................................................................6 pin configuration and function descriptions..............................7 theory of operation .........................................................................8 gain selection................................................................................8 outline dimensions ....................................................................... 10 ordering guide .......................................................................... 10 revision history 4/07revision 0: initial version
preliminary technical data ad8253 rev. pra | page 3 of 10 specifications +v s = +15 v, ?v s = ?15 v, v ref = 0 v @ t a = 25c, g = 1, r l = 2 k, unless otherwise noted. table 2. parameter conditions min typ max unit common-mode rejection ratio (cmrr) cmrr to 60 hz with 1 k source imbalance +in = ?in = ?10 v to +10 v g = 1 80 db g = 10 100 db g = 100 120 db g = 1000 120 db cmrr to 50 khz +in = ?in = ?10 v to +10 v g = 1 80 db g = 10 db g = 100 db g = 1000 db noise voltage noise, 1 khz, rti g = 1 40 nv/hz g = 10 9 nv/hz g = 100 8 nv/hz g = 1000 8 nv/hz 0.1 hz to 10 hz, rti g = 1 2.5 v p-p g = 10 2.5 v p-p g = 100 v p-p g = 1000 v p-p current noise, 1 khz 5 pa/hz current noise, 0.1 hz to 10 hz 60 pa p-p voltage offset offset rti v os g = 1, 10, 100, 1000 200 + 600/g v over temperature t = ?40c to +85c 260 + 900/g v average tc t = ?40c to +85c 1.2 + 5/g v/c offset referred to the input vs. supply (psr) v s = 5 v to 15 v 6 + 20/g v/v input current input bias current 5 30 na over temperature t = ?40c to +85c 40 na average tc 400 pa/c input offset current 5 30 na over temperature t = ?40c to +85c 30 na average tc 160 pa/c dynamic response small signal ?3 db bandwidth g = 1 10 mhz g = 10 6 mhz g = 100 3 mhz g = 1000 0.3 mhz settling time 0.01% out = 10 v step g = 1 585 ns g = 10 648 ns g = 100 ns g = 1000 ns
ad8253 preliminary technical data rev. pra | page 4 of 10 parameter conditions min typ max unit settling time 0.001% out = 10 v step g = 1 615 ns g = 10 685 ns g = 100 ns g = 1000 ns slew rate g = 1 20 v/s g = 10 25 v/s g = 100 25 v/s g = 1000 25 v/s total harmonic distortion f = 1 khz, r l = 10 k, g = 1 db gain gain range g = 1, 10, 100, 1000 1 1000 v/v gain error out = 10 v g = 1 0.03 % g = 10 0.04 % g = 100 % g = 1000 % gain nonlinearity out = ?10 v to +10 v g = 1 r l = 10 k, 2 k, 600 6 ppm g = 10 r l = 10 k, 2 k, 600 10 ppm g = 100 r l = 10 k, 2 k, 600 ppm g = 1000 r l = 10 k, 2 k, 600 ppm gain vs. temperature all gains 10 ppm/c input input impedance differential 1 g || pf common mode 1 g || pf input operating voltage range v s = 5 v to 15 v ?v s + 1.0 +v s ? 1.1 v over temperature t = ?40c to +85c ?v s + 1.1 +v s ? 1.4 v output output swing ?13.5 +13.5 v over temperature t = ?40c to +85c ?13.5 +13.5 v short-circuit current 37 ma reference input r in 20 k i in +in, ?in, ref = 0 1 a voltage range ?v s +v s v gain to output 1 0.0001 v/v digital logic digital ground voltage, dgnd referred to gnd ?v s + 4.25 0 +v s ? 2.7 v digital input voltage low referred to gnd dgnd 2.1 v digital input voltage high referred to gnd 2.8 +v s v digital input current 1 a gain switching time 1 325 ns t su see figure 2 timing diagram 20 ns t hd 10 ns t wr -low 20 ns t wr -high 40 ns
preliminary technical data ad8253 rev. pra | page 5 of 10 parameter conditions min typ max unit power supply operating range 5 15 v quiescent current, +i s 4.1 4.5 ma quiescent current, ?i s 3.7 4.5 ma over temperature t = ?40c to +85c 4.5 ma temperature range specified performance ?40 +85 c 1 add time for the output to slew and settle to calculate the total time for a gain change. timing diagram a0, a1 wr t su t hd t wr-high t wr-low 0 6287-003 figure 2. timing diagram for latched gain mode (see the timing for latched gain mode section)
ad8253 preliminary technical data rev. pra | page 6 of 10 absolute maximum ratings table 3. parameter rating supply voltage 17 v power dissipation see figure 3 output short-circuit current indefinite 1 common-mode input voltage v s differential input voltage v s digital logic inputs v s storage temperature range C65c to +125c operating temperature range 2 C40c to +85c lead temperature (soldering 10 sec) 300c junction temperature 140c ja (4-layer jedec standard board) 112c/w package glass transition temperature 140c 1 assumes the load is referenced to mid supply. 2 temperature for specifie d performance is ?40c to +85c. for performance to +125c, see the error! reference source not found. section. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum power dissipation the maximum safe power dissipation in the ad8253 package is limited by the associated rise in junction temperature (t j ) on the die. the plastic encapsulating the die locally reaches the junction temperature. at approximately 140c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ad8253. exceeding a junction temperature of 140c for an extended period can result in changes in silicon devices, potentially causing failure. the still-air thermal properties of the package and pcb ( ja ), the ambient temperature (t a ), and the total power dissipated in the package (p d ) determine the junction temperature of the die. the junction temperature is calculated as ( ) ja d a j p t t + = the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). assuming the load (r l ) is referenced to midsupply, the total drive power is v s /2 i out , some of which is dissipated in the package and some in the load (v out i out ). the difference between the total drive power and the load power is the drive power dissipated in the package. p d = quiescent power + ( total drive power ? load power ) () l out l out s s s d r v r v v i v p 2 C 2 ? ? ? ? ? ? ? ? + = in single-supply operation with r l referenced to ?v s , worst case is v out = v s /2. airflow increases heat dissipation, effectively reducing ja . in addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the ja . figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature on a 4-layer jedec standard board. 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 ?40 ?20 120 100 80 60 40 20 0 maximum power dissipation (w) ambient temperature (c) 06287-004 figure 3. maximum power dissipation vs. ambient temperature esd caution
preliminary technical data ad8253 rev. pra | page 7 of 10 pin configuration and function descriptions nc = no connect ad8253 top view (not to scale) -in 1 dgnd 2 -vs 3 a0 4 a1 5 +in vref +vs vout wr 10 9 8 7 6 figure 4. 10-lead msop (rm-10) pin configuration table 4. pin function descriptions pin no. name description 1 ?in inverting input terminal. true differential input. 2 dgnd digital ground. 3 ?v s negative supply terminal. 4 a0 gain setting pin (lsb). 5 a1 gain setting pin (msb). 6 wr write enable. 7 out output terminal. 8 +v s positive supply terminal. 9 ref reference voltage terminal. 10 +in noninverting input terminal. true differential input.
ad8253 preliminary technical data rev. pra | page 8 of 10 theory of operation 10k ? 10k ? 10k ? 10k ? ref output a3 ? in +in wr 2.2k ? 2.2k ? + v s + v s ?v s ?v s +v s ?v s +v s ?v s a1 a0 2.2k ? dgnd a1 a2 digital gain control 2.2k ? +v s ?v s +v s ?v s +v s ?v s +v s ?v s 0 6287-050 figure 5. simplified schematic the ad8253 is a monolithic instrumentation amplifier based on the classic, three op amp topology as shown in figure 5. it is fabricated on the analog devices, inc. proprietary i cmos process that provides precision, linear performance ,and a robust digital interface. a parallel interface allows users to digitally program gains of 1, 10, 100, and 1000. gain control is achieved by switching resistors in an internal, precision, resistor array (as shown in figure 5). although the ad8253 has a voltage feed- back topology, gain bandwidth product increases for gains of 1, 10, and 100 because each gain has its own frequency compensation. this results in maximum bandwidth at higher gains. all internal amplifiers employ distortion cancellation circuitry and achieve high linearity and ultralow thd. laser trimmed resistors allow for a maximum gain error of less than 0.03% for g = 1, and minimum cmrr of 120 db for g = 1000. a pinout optimized for high cmrr over frequency enables the ad8253 to offer cmrr over frequency of 80 db at 50 khz (g = 1). the balanced input reduces the parasitics that, in the past, had adversely affected cmrr performance. gain selection this section shows users how to configure the ad8253 for basic operation. logic low and logic high voltage limits are listed in the specifications section. typically, logic low is 0 v and logic high is 5 v; both voltages are measured with respect to dgnd. refer to the specifications table (table 2) for the permissible voltage range of dgnd. the gain of the ad8253 can be set using two methods. transparent gain mode the easiest way to set the gain is to program it directly via a logic high or logic low voltage applied to a0 and a1. figure 6 shows an example of this gain setting method, referred to through- out the data sheet as transparent gain mode. tie wr to the negative supply to engage transparent gain mode. in this mode, any change in voltage applied to a0 and a1 from logic low to logic high, or vice versa, immediately results in a gain change. table 5 is the truth table for transparent gain mode and figure 6 shows the ad8253 configured in transparent gain mode. figure 6. transparent gain mode, a0 and a1 = high, g = 1000
preliminary technical data ad8253 rev. pra | page 9 of 10 table 5. truth table logic levels for transparent gain mode wr a1 a0 gain ?v s low low 1 ?v s low high 10 ?v s high low 100 ?v s high high 1000 latched gain mode some applications have multiple programmable devices such as multiplexers or other programmable gain instrumentation amplifiers on the same pcb. in such cases, devices can share a data bus. the gain of the ad8253 can be set using wr as a latch, allowing other devices to share a0 and a1. figure 7 shows a schematic using this method, known as latched gain mode. the ad8253 is in this mode when wr is held at logic high or logic low, typically 5 v and 0 v, respectively. the voltages on a0 and a1 are read on the downward edge of the wr signal as it transitions from logic high to logic low. this latches in the logic levels on a0 and a1, resulting in a gain change. see the truth table listing in table 6 for more on these gain changes. figure 7. latched gain mode, g = 1000 table 6. truth table logic le vels for latched gain mode wr a1 a0 gain high to low low low change to 1 high to low low high change to 10 high to low high low change to 100 high to low high high change to 1000 low to low x 1 x 1 no change low to high x 1 x 1 no change high to high x 1 x 1 no change 1 x = dont care. upon power-up, the ad8253 defaults to a gain of 1 when in latched gain mode. in contrast, if the ad8253 is configured in transparent gain mode, it starts at the gain indicated by the voltage levels on a0 and a1 upon power-up. timing for latched gain mode in latched gain mode, logic levels at a0 and a1 have to be held for a minimum setup time, t su , before the downward edge of wr latches in the gain. similarly, they must be held for a minimum hold time of t hd after the downward edge of wr to ensure that the gain is latched in correctly. after t hd , a0 and a1 may change logic levels but the gain does not change (until the next downward edge of wr ). the minimum duration that wr can be held high is t wr -high , and t wr -low is the minimum duration that wr can be held low. digital timing specifications are listed in table 2. the time required for a gain change is dominated by the settling time of the amplifier. a timing diagram is shown in figure 8. when sharing a data bus with other devices, logic levels applied to those devices can potentially feed through to the output of the ad8253. feedthrough can be minimized by decreasing the edge rate of the logic signals. furthermore, careful layout of the pcb also reduces coupling between the digital and analog portions of the board. a0, a1 wr t su t hd t wr-high t wr-low 0 6287-053 figure 8. timing diagram for latched gain mode
ad8253 preliminary technical data rev. pr a | page 10 of 10 pr06983-0-9/07(pra) outline dimensions compliant to jedec standards mo-187-ba 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.05 0.33 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc pin 1 coplanarity 0.10 3.10 3.00 2.90 3.10 3.00 2.90 5.15 4.90 4.65 figure 9. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model temperature range package description package option branding ad8253armz 1 C40c to +85c 10-lead msop rm-10 y0k ad8253armz-rl 1 C40c to +85c 10-lead msop rm-10 y0k ad8253armz-r7 1 C40c to +85c 10-lead msop rm-10 y0k ad8253-evalz 1 evaluation board 1 z = rohs compliant part.
|
